1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display (LCD) device and a method of fabricating the LCD device.
2. Discussion of the Related Art
Flat panel display devices have begun to replace cathode-ray tubes (CRTs) for information display applications. Various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays (FEDs), and electro-luminescence displays (ELDs) have been developed to replace CRTs. Of these types of flat panel displays, LCD devices have many advantages, such as high resolution, light weight, thin profile, compact size, and low voltage power supply requirements.
In general, an LCD device includes two substrates that are spaced apart and opposed to each other with a liquid crystal material interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal material. Alignment of the liquid crystal molecules in the liquid crystal material changes proportionally with the intensity of the induced electric field in the direction of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the induced electric field.
Recently, active matrix type LCD devices, which include thin film transistors (TFTs) and pixel electrodes arranged in matrix form, have been commonly used. Hydrogenated amorphous silicon (a-Si:H) has been used as an active layer for the TFT because of its low temperature applications as well as its relatively low price. However, because the atoms in the hydrogenated amorphous silicon are randomly arranged, the bonds between the silicon atoms are weak and dangling. Accordingly, when light is irradiated or electric field is induced, the silicon atom is in a quasi-stable state, thereby making the TFT unstable. The weak bonds also cause poor electric properties. For example, the field effect mobility value is as low as 0.1 to 1.0 cm2/V·sec. Therefore, TFTs having amorphous silicon cannot reliably be used as a driving circuit.
In contrast, poly-crystalline silicon can be used for a driving circuit since poly-crystalline silicon has higher field effect mobility than amorphous silicon. Therefore, compact-sized LCD devices can be made when a driving circuit using poly-crystalline silicon is formed directly on the substrate.
FIG. 1 is a plan view illustrating an array substrate for an LCD device having a driving circuit formed directly thereon according to a related art. As illustrated in FIG. 1, a substrate 2 of the related art LCD device includes a display region “D” and a non-display region “N.” In the display region D, a plurality of pixel regions “P” are arranged in matrix form. In each pixel region P, a pixel TFT “T” and a pixel electrode 78 are formed.
Gate lines “GL” extend along a first direction, and data lines “DL” extend along a second direction perpendicular to the first direction. The intersecting regions of the gate and data lines GL and DL define the pixel regions P.
In the non-display region N, gate and data driving portions “GP” and “DP” are formed. The gate driving portion GP is disposed on a first side of the substrate 2 and supplies gate signals to the gate lines GL. The data driving portion DP is disposed on a second side of the substrate 2 and supplies data signals to the data lines DL. The gate and data driving portions GP and DP are connected to signal input terminals “OL.” The signal input terminals OL transfer external signals from an external driving circuit, such as control, gate, and data signals, to the gate and data driving portions GP and DP. The gate and data driving portions GP and DP adjust the gate and data signals from the external driving circuit based on the control signals, and supply the gate and data signals to each pixel region P. To do this, the gate and data driving portions GP and DP include a CMOS (a complementary metal-oxide semiconductor) as an inverter. The CMOS used as the driving device includes an n-type TFT using an electron as a carrier, and a p-type TFT using a hole as a carrier. The n-type and p-type TFTs are formed directly on the substrate 2 using the poly-crystalline silicon. In the related art LCD device, the pixel TFT “T” and the driving device (i.e., the CMOS) are formed with the same processes.
FIG. 2 is a plan view illustrating a pixel of an array substrate for an LCD device according to the related art. As illustrated in FIG. 2, gate and data lines GL and DL cross each other to define a pixel region P on a substrate 2. A pixel TFT T is disposed at a crossing portion of the gate and data lines GL and DL. The pixel TFT T includes an active layer 14 made of poly-crystalline silicon, a gate electrode 32, and source and drain electrodes 70 and 72, respectively, contacting the active layer 14. A pixel electrode 78 contacting the drain electrode 72 is disposed in the pixel region P. A storage capacitor “CST” is also disposed in the pixel region P. The storage capacitor CST includes a poly-crystalline silicon pattern 76 as a first electrode and a storage line 34 extending across the pixel region P as a second electrode.
Hereinafter, a method of fabricating the array substrate for the related art LCD device will be explained. FIGS. 3A and 3B are cross-sectional views illustrating a driving region and a pixel region, respectively, of an array substrate for the related art LCD device in a first mask process. The driving region is a region where the driving device, i.e., the CMOS, of the gate and data driving portions of FIG. 1 is formed.
As illustrated in FIGS. 3A and 3B, a buffer layer 4 is formed on an entire surface of the substrate 2. The buffer layer 4 is made of silicon oxide (SiO2). Then, with a first mask, active patterns 10, 12, 14, and a poly-crystalline silicon pattern 16 are formed on the buffer layer 2. In particular, first and second active patterns 10 and 12 are formed in the n-type and p-type driving regions “NR” and “PR” of the driving region “DA,” respectively, and a third active pattern 14 is formed in a switching region “C” of the pixel region P. The poly-crystalline silicon pattern 16 is formed in a storage region “ST” of the pixel region P. The poly-crystalline silicon pattern 16 is extended from the third active pattern 14.
FIGS. 4A and 4B are cross-sectional views illustrating a driving region and a pixel region, respectively, of an array substrate for the related art LCD device in a second mask process. First, a photoresist is deposited on the substrate 2 to form a photoresist layer. Then, with a second mask, the photoresist layer is patterned to form first, second, and third photoresist patterns 20, 22, and 24 on the first, second, and third active patterns 10, 12, and 14, respectively, as illustrated in FIGS. 4A and 4B. The poly-crystalline silicon pattern 16 is left exposed. Then, the poly-crystalline silicon pattern 16 is doped with n+ (high concentration n-type) or p+ (high concentration p-type) impurity ions. The doped poly-crystalline silicon pattern 16 functions as a first electrode of the storage capacitor (CST of FIG. 2). Thereafter, the first to third photoresist patterns 20, 22 and 24 are removed.
FIGS. 5A and 5B are cross-sectional views illustrating a driving region and a pixel region, respectively, of an array substrate for the related art LCD device in a third mask process. As illustrated in FIGS. 5A and 5B, a gate insulator 26 is formed on the entire substrate 2 having the active patterns 10, 12, and 14. The gate insulator 26 is made of an inorganic insulating material, such as silicon nitride (SiNx) and silicon oxide (SiO2). Then, a conductive material is deposited on the gate insulator 26 to form a conductive material layer. With a third mask, the conductive material layer is patterned to form first, second, and third gate electrodes 28, 30, and 32, corresponding to the first, second, and third active patterns 10, 12, and 14, respectively. The conductive material includes aluminum (Al) and aluminum alloy (AlNd). In the same process of forming the gate electrodes 28, 30, and 32, a storage line 34 overlapping the poly-crystalline silicon pattern 16 is formed. The storage line 34 and the poly-crystalline silicon pattern 16 overlapping each other define the storage capacitor CST.
The first to third active patterns 10, 12, and 14 include active regions “A1,” “A2,” and “A3,” respectively, at center portions, source regions “S1,” “S2,” and “S3,” respectively, at first side portions, and drain regions “D1,” “D2,” and “D3,” respectively, at second side portions. In particular, the first and third active patterns 10 and 14 further include lightly-doped drain (LDD) regions “F1,” “F2,” “F3,” and “F4.”
The first to third active regions A1, A2, and A3 correspond to the first to third gate electrodes 28, 30, and 32, respectively. The first and second LDD regions F1 and F2 are disposed between the first active region A1 and the first source region S1 and between the first active region A1 and the first drain region D1, respectively. The third and fourth LDD regions F3 and F4 are disposed between the third active region A3 and the third source region S3 and between the third active region A3 and the third drain region D3, respectively. The substrate 2 is doped with n− (low concentration n-type) impurity ions. Accordingly, the source regions S1, S2, and S3, the drain regions D1, D2, and D3, and the LDD regions F1, F2, F3, and F4 are doped with the n− impurity ions.
FIGS. 6A and 6B are cross-sectional views illustrating a driving region and a pixel region, respectively, of an array substrate for the related art LCD device in a fourth mask process. A photoresist is deposited on the substrate 2 having the n− doped active patterns 10, 12, and 14. With a fourth mask, the photoresist layer is patterned to form first, second, and third photoresist patterns 36, 38, and 40 covering the first, second, and third gate electrodes 28, 30, and 32, respectively, as illustrated in FIGS. 6A and 6B.
More particularly, the first photoresist pattern 36 covers the first active region A1 and the first and second LDD regions F1 and F2. The second photoresist pattern 38 covers the entire second active pattern 12. The third photoresist pattern 40 covers the third active region A3 and the third and fourth LDD regions F3 and F4. In other words, the first source and drain regions S1 and D1 and the third source and drain regions S3 and D3 are not covered by the first and third photoresist patterns 36 and 40.
Then, the substrate 2 is doped with n+ impurity ions. Accordingly, the first source and drain regions S1 and D1 and the third source and drain regions S3 and D3 are doped with n+ impurity ions to function as ohmic contact layers. Then, the first to third photoresist patterns 36, 38, and 40 are removed.
FIGS. 7A and 7B are cross-sectional views illustrating a driving region and a pixel region, respectively, of an array substrate for the related art LCD device in a fifth mask process. As illustrated in FIGS. 7A and 7B, first and second photoresist patterns 42 and 44 are formed on the n-type driving region NR and the pixel region P using a fifth mask. Particularly, the first photoresist pattern 42 covers the entire first active pattern 10, and the second photoresist pattern 44 covers both the third active pattern 14 and the poly-crystalline silicon pattern 16. The second active pattern 12 is left exposed. Then, the substrate 2 is doped with p+ impurity ions. Accordingly, the second source and drain regions S2 and D2 are doped with p+ impurity ions to function as ohmic contact layers. Then, the first and second photoresist patterns 42 and 44 are removed.
FIGS. 8A and 8B are cross-sectional views illustrating a driving region and a pixel region, respectively, of an array substrate for the related art LCD device in a sixth mask process. An interlayer insulating film 46 is formed on the substrate 2 after the p+ doping process was conducted. With a sixth mask, the gate insulator 26 and the interlayer insulating film 46 are patterned to form first and second contact holes 50 and 52 exposing the first source and drain regions S1 and D1, respectively, third and fourth contact holes 54 and 56 exposing the second source and drain regions S2 and D2, respectively, and fifth and sixth contact holes 58 and 60 exposing the third source and drain regions S3 and D3, respectively, as illustrated in FIGS. 8A and 8B.
FIGS. 9A and 9B are cross-sectional views illustrating a driving region and a pixel region, respectively, of an array substrate for the related art LCD device in a seventh mask process. With a seventh mask, first, second, and third source electrodes 62, 66, 70 and first, second, and third drain electrodes 64, 68, and 72 are formed as illustrated in FIGS. 9A and 9B. The first source and drain electrodes 62 and 64 contact the first source and drain regions S1 and D1 through the first and second contact holes (50 and 52 of FIG. 8A). Similarly, the second source and drain electrodes 66 and 68 contact the second source and drain regions S2 and D2 through the third and fourth contact holes (54 and 56 of FIG. 8A), and the third source and drain electrodes 70 and 72 contact the third source and drain regions S3 and D3 through the fifth and sixth contact holes (58 and 60 of FIG. 8B). Using the above-described processes, an n-type TFT, a p-type TFT, and a pixel TFT are formed in the n-type region NR, the p-type region PR, and the pixel region P, respectively.
FIGS. 10A and 10B are cross-sectional views illustrating a driving region and a pixel region, respectively, of an array substrate for the related art LCD device in a eighth mask process. As illustrated in FIGS. 10A and 10B, a passivation layer 74 is formed on the substrate 2 having the source and drain electrodes 62, 64, 66, 68, 70, and 72. Then, with a eighth mask, the passivation layer 74 is patterned to form a drain contact hole 76 exposing the third drain electrode 72.
FIGS. 11A and 11B are cross-sectional views illustrating a driving region and a pixel region, respectively, of an array substrate for the related art LCD device in a ninth mask process. A transparent conductive material is deposited on the passivation layer 74. Then, with a ninth mask, the transparent conductive material layer is patterned to form a pixel electrode 78 in the pixel region P as illustrated in FIGS. 11A and 11B. The pixel electrode 78 contacts the third drain electrode 72 through the drain contact hole 76.
As explained above, both the driving device having the n-type and p-type TFTs and the pixel TFT using the poly-crystalline silicon are formed on the same substrate using the same processes. However, the method of fabricating the related art array substrate needs many mask processes, thereby increasing the time and cost for fabricating the array substrate according to the related art.